1. Field of the Invention
The invention relates to memories, and more particularly to a Dynamic Random Access Memory (DRAM).
2. Description of the Related Art
A low power double data rate (LPDDR) DRAM is a type of double data rate synchronous DRAM for mobile computers. The circuit design of an LPDDR DRAM is modified to reduce overall power consumption thereof. A new JEDEC standard JESD209-2E is referred to as an LPDDR2. The LPDDR2 DRAM operates at a low supply voltage of 1.2V. In comparison to LPDDR2 DRAM, LPDDR3 DRAM offers a higher data rate, greater bandwidth and power efficiency, and higher memory density.
Specifically, in LPDDR2 DRAM and LPDDR3 DRAM, the LPDDR DRAM is coupled to a DRAM controller via a control and address bus. The control and address (CA) bus comprises 10 control and address lines coupled between the DRAM controller and the DRAM. The control and address lines operate at a frequency which is double of that of a clock signal and therefore have a double data rate. The DRAM controller sends commands and addresses to the DRAM via the control and address bus, and the DRAM then accesses the commands and the addresses from the control and address bus according to the clock signal.
The phase difference between the clock signal and control and address signals transmitted via the control and address bus must be kept at constant level. If the phase difference between the clock signal and the control and address signals varies with time, because the operating frequency of the control and address bus is double of that of the clock signal, when the DRAM accesses the data of the control and address signals according to the clock signal with a changed phase, the DRAM tends to obtain error data due to the varied phase difference. The phases of the clock signal and control and address signals transmitted via the control and address bus, however, changes with temperature, the operating voltage, and manufacture process of the DRAM controller. Thus, a system which automatically adjusts the phases of the clock signal and the control and address signals to keep the phase difference at constant levels is required.